In mass data storage supports, as for example hard disks, floppy disks, CDs, tape streamers and the like, digital data are stored, in practice, by physically recording on the support only the logic "1", and by "spacing" them by "segments" of a recording track, the length of which is proportional to the number of logical "0" present between successive "1".
Considerations on the dynamic character typical of rotating supports or generally of translating supports, impose a minimum value of the separation distance between adjacently recorded "1". In fact, if two successive "1" are physically recorded one next to the other on the support, inevitable interferences between the two recorded peaks detected in reading the data which is on the support, can cause uncertainties and errors due to practical limitations of the discriminating capabilities of the reading pick-ups.
Another common peculiarity of these mass data storage systems is represented by the fact that the sampling clock signal, used in the write/read channels, cannot be derived from a fixed system's clock. Necessarily it must be a clock signal that is derived or extracted directly from the incoming serial stream of data, the speed of which may often vary. For example, in the case of a hard disk, data recorded on outer tracks may be written and read at a higher linear speed than data written and read on inner concentric tracks. Generally, in this as in other applications, a variable frequency clock signal, synchronous with the serial stream of data (pulses), is generated by detecting transitions in the coded stream of pulses that represents the succession of digital data, for example by employing a common phase-locked, ring circuit (PLL), cooperating with a voltage controlled oscillator (VCO). Where the need exists for self-generating a synchronous, variable frequency, clock signal, there may be a limit to the maximum tolerable "distance" between any two successively recorded logic "1". In fact, if successive transitions occur after an excessively long interval of time, synchronism of the frequency of the self-generated clock signal, "phase-locked" with the pulse stream, can be partially lost. Thus this situation would introduce, also in this case, conditions of indiscrimination of the correct sampling instant and therefore the possibility of errors during reading.
These "dynamic" limits in the operation of these systems are commonly overcome by employing special coding systems for the data being transferred, which ensure a certain minimum number of "0" and a certain maximum number of "0" between any two successive "1" of a coded binary data stream.
There are different coding protocols of this type. For example in the RLL(2,7) coding (an acronym for Run Length Limited), the values 2 and 7 indicate the minimum (2) number and the maximum (7) number, respectively, of "0" between two successive "1". In the RLL(1,7) system, the two values indicate the minimum number (1) and the maximum number (7) of "0", that can be present between any two successive "1" of a coded binary data.
Of course, the use of a particular coding of the serial data stream, for example from and to a rotating mass storage support, or also from and to a different type of peripheral having dynamic characteristics of operation similar thereto, implies the use of special coding and decoding circuits of the serial stream of digital data.
A peculiarity common to these as well as to other coding/decoding systems is represented by the fact that the "frequencies" of the input and output serial data streams are different from each other. To a certain X number of bits of a decoded data serial signal, commonly of the so-called NRZ type (an acronym of Non-Return-to-Zero), correspond a greater Y number of bits (Y=X+z, where z.gtoreq.1) of a coded data serial signal. For example, to three bits (pulses) of the coded signal may correspond two bits (pulses) of an NRZ stream of decoded data. This fact implies that, during a reading phase, a certain time base frequency (base clock) VCO, is extracted from the sequence of transitions of the input coded signal, for example by the use of a PLL circuit, and from said base clock other fractionary frequency clocks signals are derived. The clock signal VCO, synchronous with the coded serial stream, is used as the control (sampling) clock signal of a shift register to which the coded serial signal is fed. In the case already taken into consideration, the ratio between the equivalent number of bits of the coded serial stream and of the decoded serial stream is equal to 3:2(1.5). Therefore, the base clock signal VCO, derived from the transitions of the coded input signal, may be used for deriving a first fractionary frequency clock signal VCO/1.5, for sampling the decoded output signal, and a second fractionary frequency clock signal VCO/3, which is employed in the timing and synthesizing functions that must be necessarily performed by the decoding logic circuitry of the decoder.
Typically, a decoder of this type employs two decodification combinative logic networks. In the case of a decoder designed for handling an n number of bits, a first logic network processes the n-bits present at the n taps of a shift register to which the coded input signal is fed, under the control of the synchronous extracted clock signal VCO, and produces a first decoded signal. The signal produced by the first logic network is timed, by employing for the purpose a flip-flop that is sampled at the fractionary frequency of the first fractionary clock signal, in the example VCO/1.5. The so re-timed signal is fed to an input of a second combinative logic network. Said second combinative logic network processes a fractionary number of the n number of bits, picked up from the respective taps of the input shift register, the first decoded signal produced by the first combinative logic network and the second fractionary frequency clock signal (VCO/3 according to the example). This allows to re-synthesize the re-timed signal, produced by the first network and to produce a second decoded signal at the output of the second combinative logic network. Said second decoded signal is fed to a second output flip-flop sampled at the frequency of the first fractionary frequency clock signal, and produces a decoded NRZ output stream.
A decoder of this type together with an improved decoder are described in the co-pending patent application Ser. No. 08/285,918, which has been incorporated by reference. Said improved decoder incorporates timing, and multiplexing circuits for the first decoded signal. In cooperation with storing latches of the fractionary number of bits that are processed by the second logic network, said circuits permit to double the operating frequency of the decoder, for the same fabrication technology of the combinative logic networks.
Then, circuits "downstream" of the decoder must convert the serial stream of NRZ data in binary words, for example of 8 bits, that may thereafter be transferred toward a central processing unit, through parallel interfaces. This conversion of the data stream is commonly assisted by a microprocessor that supervises the serial-to-parallel conversion and the routing of the decoded bytes toward a support memory.
The solution of employing a decoder that instead of producing a single NRZ output stream, produces two output streams, that is a dual output stream, respectively a first NRZ0 data stream and a second NRZ1 data stream, is known. For the same frequency of the coded data signal present at the input of the decoder, the use of a dual-bit NRZ decoder permits to employ circuits for converting the decoded NRZ serial signal into a binary parallel signal capable of operating at half the frequency that would be necessary for handling a single-bit decoded NRZ output stream. Notwithstanding that the required duplication of the downstream conversion networks will not produce a substantial global energy saving, it is possible to employ "slower" integrated circuits for realizing the converting networks, that is devices fabricated with less sophisticated technologies and therefore less expensive. The saving increases with the frequency of the input serial data stream. In many cases, the possibility of employing devices that can be fabricated with different technologies, permits also to optimize performances of the respective subsystems.
In general, the choice of a single-bit NRZ decoder or of a dual-bit NRZ decoder, depends on design choices of the user of the integrated devices, that is of the manufacturer of the hardware apparatus. For need of utility, the operating mode of a decoder should be programmable by the user, according to his needs and/or in function of mutating operating conditions of the whole hardware system.